Transistor and method for making a transistor on a sige/soi substrate

ABSTRACT

The present invention relates to process for producing a transistor of MOS type, comprising the following stages:  
     a) providing a substrate comprising a thin layer of silicon ( 26 ), integral with an insulating support ( 14 ), and covered with a superficial layer ( 28 ) of a semi-conductor material,  
     b) local etching of the superficial layer to expose the silicon layer in at least one channel region,  
     c) formation of an insulated grille ( 50 ) above the silicon layer in the channel region, and formation of a source and a drain on either side of the channel region, the source and drain extending in the layer of silicon and in the superficial layer.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority based on International PatentApplication No. PCT/FR02/02523, entitled “Transistor and Process forProducing a Transistor on a SIGE/SOI Substrate” by Jean-Pierre Joly,which claims priority of French application no. 01 09665, filed on Jul.19, 2001, and which was not published in English.

TECHNICAL FIELD

[0002] The present invention relates to a field effect transistor of MOStype (transistor with insulated gate) and a process for producing saidtransistor.

[0003] The invention can be applied in general in the fields ofmicroelectronics and commutation electronics. It is aimed in particularat the production of transistors capable of functioning at highfrequencies.

PRIOR ART

[0004] Rapid-switching Transistors, that is, transistors capable offunctioning at high frequency, generally have short and sufficientlyfine channels to authorize their full depletion. Also, in producingthem, use is preferably made of substrates of silicon-on-insulator type(SOI). A particular feature of these substrates is a thin layer ofsilicon, separated from a solid substrate by an embedded insulatinglayer of, for example, silicon oxide. The channel of the transistor, aswell as the source and the drain, are then formed in the thin layer.

[0005] A technique well-known for manufacturing substrates ofsilicon-on-insulator type consists of transferring to a receiversubstrate, comprising a superficial layer of silicon oxide, a block ofdonor silicon, and fracturing this block along an embrittlement zone todetach a thin layer from it. The thin silicon layer remains integralwith the layer of silicon oxide, which is thus embedded. Even thoughother solutions can be offered, the embrittlement zone of the block ofsilicon is preferably made by implanting hydrogen and/or rare gas ions.Therefore, the thickness of the thin layer is dictated by the depth,therefore the implantation energy, of the embrittlement zone. Now, iteventuates that this technique does not produce layers of siliconwhereof the thickness does not exceed a few nanometers and which may becontrolled with a good precision. Indeed after the transfer, the siliconlayer has some roughness, or at least some surface defects.

[0006] In order to guarantee a better precision of the thickness of thesilicon layer, as well as a good surface quality, another techniqueconsists of having the silicon layer grow by epitaxy on a layer of amaterial such as SiGe, before it is transferred from a donor substrateto the receiver substrate. The transfer takes place by leaving the thinsilicon layer integral with all or part of the layer of SiGe, andpossibly a part of the donor substrate. In other words, theembrittlement zone is not formed in the silicon, but in the underlyinglayer of SiGe or substrate. Following transfer the remainder of thelayer of SiGe, as well as possibly the remainder of the donor substrate,are taken off by etching. This etching procedure is carried out usingselective etching agents relative to the silicon so as to be able toutilize the thin silicon layer as an etching stop layer.

[0007] In the end of etching, the thin silicon layer which is integralwith the layer of oxide of the receiver substrate has a completely freeface. Accordingly, the thickness of the layer is not dictated by thefracture of a donor substrate, but by epitaxy. Now, epitaxy producesparticularly thin layers and permits their thickness to be perfectlycontrolled.

[0008] The thinness of the silicon layer also allows the length of thechannel to be reduced and thus allows the transistor to be miniaturized.In addition, a very thin layer of silicon can result in ‘bi-dimensional’transistors with very strong depletion of the channel. The frequencyperformances of the transistors are thus improved. On the other hand andstill because of the low thickness of the silicon layer the accessresistance to the source and drain tends to increase and constitutes anew limit of the performances of the transistors.

[0009] An illustration of the prior art can be found, for example, inthe documents (1) and (2), of which the references are specified in theend of the present description.

DESCRIPTION OF THE INVENTION

[0010] The object of the invention is to propose a transistor and itsproduction process, which does not have the difficulties or limitationsmentioned hereinabove.

[0011] An aim in particular is to propose a process, which controls thethickness and the length of the channel with high precision.

[0012] Another aim still is to propose a transistor with reduced accessresistances to the source and the drain.

[0013] To attain these aims, the object of the invention more preciselyis a process comprising the following stages:

[0014] a) providing a substrate comprising a thin layer of silicon,integral with an insulating support, and covered with a superficiallayer of a semi-conductor material,

[0015] b) locally etching the superficial layer to expose the siliconlayer in at least one channel region,

[0016] c) forming an insulated gate above the silicon layer in thechannel region, and forming a source and a drain on either side of thechannel region, the source and drain extending in the layer of siliconand in the superficial layer.

[0017] In this process the so-called superficial layer is preferably alayer having a unit cell parameter close to that of silicon. It hasseveral functions. A first function is to authorize selective etchingrelative to the silicon. A second function is to increase the volume ofthe source and the drain, by raising them, so as to reduce their accessresistance. Finally, whenever it has a unit cell parameter close to thatof silicon, a third function is to favor epitaxial growth of a thinsilicon layer, with a controlled thickness.

[0018] The superficial layer is preferably a layer of SiGe. However,other semi-conductor materials such as, for example, SiC or alloys ofSi_(x)Ge_(y)C_(1-x-y), Ga_(x)P_(1-x) or Ga_(x)In_(1-x)N_(y)As_(1-y) typecan also be appropriate.

[0019] The local etching of the superficial layer comes down to making awell in this layer at the place where the future gate will be formed. Itshould be noted that, even though the description essentially refers tothe manufacture of a single transistor, a plurality of transistors canbe produced concomitantly. In this case, etching is done according to apattern allowing exposure of the thin layer in a plurality of channelregions, each of these regions then being provided with a gate, andlinked to the source and the drain.

[0020] The etching of the superficial layer is preferably a dryanisotropic etching. However, when the silicon layer is particularlythin, or when any alteration thereto is to be avoided, it is possible tocarry out a first dry anisotropic etching, and second wet etching, withthe dry etching being interrupted before complete elimination of thesuperficial layer in the channel region. The second etching, which has aselectivity higher than that of the first etching, is continued andstopped on the silicon layer.

[0021] In effect, wet etchings generally have better selectivity thandry etchings, but are often isotropic.

[0022] The source and drain are formed not only in the thin layer ofsilicon, but also in overlying regions of the superficial layer, on bothsides of the channel. Even though other techniques, such as diffusion,can be used, the regions of source and drain are preferably formed byimplantation of doping impurities. The implantation can followed bythermal activation treatment.

[0023] To obtain a perfect alignment of the source and drain with thegate, the latter can be formed before the source and drain, and made useof as an implantation mask. In this case however, the gate is capable ofbeing subjected to the activation treatment. A selection of refractorymaterials for the gate effectively avoids this constraint. When it hasto undergo thermal treatment, the gate can be made, for example, ofpolycrystalline silicon, or of a more fragile material, such as copper,but protected by a refractory material.

[0024] According to an improvement, producing the gate can also comprisethe following stages:

[0025] formation of a bogus gate on the layer of silicon in the channelregion,

[0026] implantation of doping impurities in the layer of silicon and thesuperficial layer, by using the bogus gate as an implantation mask, and

[0027] replacement of the bogus gate by a definitive gate, insulated bya gate dielectric layer.

[0028] As the gates are always formed in the well obtained by etchingabove the channel region, the source and drain preserve their alignmentproperties during replacement of the bogus gate by the definitive gate.In addition, the materials of the bogus gate and of the definitive gatecan be selected more freely as a function of possible productionconstraints. For example, the bogus gate can be made of a materialcapable of fully resisting the thermal constraints of a possibleactivation treatment of doping impurities. Moreover, the material of thedefinitive gate, free of any thermal constraint, can be selected, forexample, as a function of its work function in view of a low thresholdvoltage of the transistor.

[0029] According to a particular embodiment of the invention, deposit ofthe gate material, and especially deposit of the material of thedefinitive gate, can be followed by one or several planarazingprocedures with stop on, or in, the so-called superficial layer.Planarizing produces a flush damascene gate.

[0030] Stage a) of the process essentially comprises providing asubstrate for producing the transistor. It can comprise, for example:

[0031] formation, on a first substrate, of the superficial layer made ofa material having a unit cell parameter close to silicon,

[0032] formation, by epitaxy, of a thin layer of silicon on theso-called superficial layer, and

[0033] transfer of the thin silicon layer and at least a part of thesuperficial layer on an insulating support, by making the thin layer ofsilicon integral with said insulating support.

[0034] The insulating support can be a bulk support, such as a block ofglass or sapphire, but can also be a simple insulating layer integralwith a substrate which is not necessarily so. For example, it can be alayer of silicon oxide covering a block of bulk silicon.

[0035] The invention finally relates to a field-effect transistorcomprising:

[0036] a channel formed in a thin layer of monocrystalline silicon,

[0037] regions of source and drain, extending on both sides of thechannel in the silicon layer and in a superficial semi-conductor layercovering the layer of silicon, the semi-conductor layer having a unitcell parameter close to silicon, and

[0038] an insulated gate, disposed above the channel, the gate beingflush so as to brush the superficial layer.

[0039] Other characteristics and advantages of the invention will emergefrom the following description, with reference to the figures of theattached drawings.

[0040] This description is given purely by way of illustration andnon-limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041]FIG. 1, illustrates, in the form of schematic sections, donor andreceiver substrates, for producing a substrate suitable for implementinga process according to the present invention.

[0042]FIGS. 2 and 3 are diagrammatic sections of a substrate obtainedfollowing the process stage corresponding to FIG. 1, and illustrate anetching stage for defining a channel region of a transistor.

[0043]FIG. 4 is a diagrammatic section of the substrate obtainedfollowing the process stage corresponding to FIG. 3, and illustratesproduction of a source and a drain of the transistor.

[0044]FIG. 5 is a diagrammatic section of the substrate obtainedfollowing the process stage corresponding to FIG. 4, and illustratesproduction of a source and a drain of the transistor.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0045] In the following description, identical, similar or equivalentcomponents of the different figures are marked by the same referencenumerals to facilitate the transfer between the figures. In addition,and in the interests of clarifying the figures, all the elements are notrepresented according to a uniform scale.

[0046]FIG. 1 illustrates the formation of a substrate adapted to themanufacture of a transistor according to the present invention. A firstreceiver substrate 10 comprises a support block 12, made of bulksilicon, covered with a layer of silicon oxide 14. The layer of siliconoxide, utilized for its electrical insulation properties, constitutesthe ‘insulating support’, which is still alluded to. By way of variant,the support block covered by an insulating layer can be replaced by ablock of bulk insulating material.

[0047] A second substrate, designated by donor substrate, likewisecomprises a support block 20, and on this block, a layer of SiGe 28, anda thin layer of silicon 26, preferably monocrystalline. The thin layerof silicon 26 is formed by epitaxy on the layer of SiGe, so as toprecisely control its thickness. The latter is, for example between 1and 20 nm.

[0048] In the example illustrated by the figures, and described here,the SiGe is selected especially for its property for having a unit cellparameter, which is sufficiently close to silicon to allow growth of acrystalline layer of good quality, and for its property of being able tobe etched selectively relative to silicon.

[0049] Reference 29 designates an embrittlement zone formed in the layerof SiGe. It is formed, for example, by ionic implantation.

[0050] An arrow R indicates the transfer of the donor substrate 20 ontothe receiver substrate 10. The transfer comprises fixing the thin layer26 against the layer of silicon oxide 14. The latter acts as insulatingsupport. The fixing can take place with or without intermediarymaterial; for example this can be a bonding by direct molecularadhesion.

[0051] The transfer of the donor substrate onto the receiver substrateis followed by fracture of the donor substrate, along the embrittlementzone 29. The effect of the fracture is to detach the thin silicon layer,from now on integral with the receiver substrate, and all or part of thelayer 28 of SiGe covering the layer of silicon. In this respect, thelayer of SiGe is still designated by ‘superficial layer’. Theembrittlement zone 29 can optionally be formed outside the layer ofSiGe, for example, in the support block 22. However, it is important tonote that the embrittlement zone does not delimit the thin siliconlayer, taken separately. Thus, during its transfer to the receiversubstrate the thin layer of silicon 26 is in no way modified.

[0052] As shown in FIG. 2, after fracture and elimination of theremaining part of the donor substrate, an etching mask 30 is formed onthe free face of the superficial layer 28. This is a resin mask. Themask 30 exhibits an opening 32 corresponding to emplacement of thechannel of a transistor, which is to be formed on the substrate.Although the figures are limited to the realization of a singletransistor, a plurality of transistors can be formed on the samesubstrate. In this case, the layer of etching mask has an openingcorresponding to the channel of each transistor to be produced.

[0053] The superficial layer 28 is subjected to a first anisotropicetching, through the opening 32 of the mask layer. This is a dryetching. In this particular example an atmosphere of active gas CF4 at10 sccm, mixed with nitrogen at 200 sccm, at a pressure of 1 Torr isused. At least one of the parameters of the dry etching, for example itsduration, is selected to interrupt the etching of the superficial layer28 of SiGe before the underlying thin layer of silicon 26 is reached.

[0054] The first etching is followed by a second wet, isotropic etching.The utilized etching agents are selected so as to selectively eliminatethe SiGe relative to the silicon. Still by way of example a mixture ofHNO₃, H₂O and HF can be used which, according to the concentration ofgermanium of the superficial layer, yields selectivities of the order of100. This subject can be referred to in document (3) whereof thereferences are specified at the end of the description. The very goodselectivity of the second wet etching helps to perfectly conserve thethickness and the surface quality of the thin silicon layer 26.

[0055] As shown in FIG. 3, the second etching is followed up with stopon the thin layer of silicon 26. The latter is exposed at the bottom ofa well 34 of which the lateral sides are adjusted on the opening 32 ofthe etching mask. More precisely, the upper part of the sides is alignedvertically to the opening 32, while the lower part, in the vicinity ofthe thin layer, exhibits a slight splaying. This splaying is due to theisotopic character of the second etching.

[0056] The splaying can be avoided by performing one or severalexclusively anisotropic etchings. However, the anisotropic etchings havea lesser selectivity, and therefore must be controlled with greater careto preserve the layer of silicon 26.

[0057]FIG. 4 shows the realization of the source and drain.

[0058] At first, a bogus gate 40, for example made of a material such assilicon nitride, is formed in the previously etched well. The bogus gateis flush and brushes the surface of the superficial layer 28.

[0059] This can be attained by depositing the material of the gate onthe entire surface of the substrate, with adequate thickness to fill upthe well, then by planarizing, for example mechano-chemical polishing,with stop on or in the superficial layer 28.

[0060] The substrate is then subjected to an implantation D of dopingimpurities using the bogus gate as implantation mask. Implantation takesplace in the thin layer of silicon 26 and in the superficial layer ofSiGe 28. It extends on both sides of the bogus gate to form a source 42and a drain 44. The bogus gate protects an underlying portion of thethin layer making up the channel 46 of the transistor. The source anddrain are thus self-aligned on the bogus gate 40 and thus on the channel46.

[0061] An implantation mask, not illustrated, can optionally be providedto limit the extension of the source and drain or to define their formoutside the transistor.

[0062] The implantation of the doping impurities is followed by thermalactivation treatment. Thermal treatment also allows the dopingimpurities to be diffused and the electric resistance of the source anddrain to be minimized, especially at the Si/SiGe interface.

[0063]FIG. 5 shows replacement of the bogus gate 40 by a definitive gate50. The bogus grille is eliminated, via selective etching, to re-openthe well. This operation is followed by formation of an insulating layerof gate 52, then of a gate 50.

[0064] The insulating layer of gate 52, formed by deposit or byoxidation, carpets the walls of the well so as to insulate the gate fromthe channel 46, but also from the source and drain 42, 44. As for thebogus gate, the formation of the definitive gate comprises the depositof a material followed by planarization. The definitive gate is thusflush and likewise brushes the surface of the superficial layer 28. Asthe definitive gate occupies the location of the bogus gate, the sourceand drain remain self-aligned on the definitive gate. In addition, thedefinitive gate, in this embodiment example, does not undergo thermaltreatment. It is made, for example, of copper or W or a TiN/Cu bi-layer.

[0065] According to a variant, the definitive gate can also be formeddirectly and this gate can be used as an implantation mask of the sourceand drain. Then use of a bogus gate is not useful. In this case, andwhen the implanted regions are to be subjected to thermal treatment, thegate is preferably made of a refractory conductive material such aspolycrystalline silicon or a silicide, for example tungsten silicide.

[0066] Cited Documents

[0067] (1) FR-A-2 774 214

[0068] (2) K. D. Hobart, Conference abstract NATO Advanced ResearchWorkshop, ‘Progress in SOI structures and device operating at extremeconditions’, pp. 63-64.

[0069] (3) J. Electrochem. Soc. Vol. 139, n° 10, Oct. 1992, “Selectiveremoval of Si_(1-x)Ge_(x), from (100) si using HNO₃ and HF”, D. J.Godbey, A. H. Krist, K. D. Hobart, and M. E. Twigg.

1. A process for producing a transistor of MOS type, comprising thefollowing stages: a) providing a substrate comprising a thin layer ofsilicon (26), integral with an insulating support (14), and covered witha superficial layer (28) of a semi-conductor material, b) local etchingof the superficial layer (28) to expose the silicon layer in at leastone channel region; c) formation of an insulated gate (50) above thesilicon layer (26) in the channel region, and formation of a source anda drain (42, 44) on either side of the channel region, the source anddrain extending in the layer of silicon and in the superficial layer. 2.The process as claimed in claim 1, wherein the superficial layer (28)has a unit cell parameter close to silicon.
 3. The process as claimed inclaim 1, wherein stage c) comprises: formation of a bogus gate (40) onthe layer of silicon in the channel region, implantation of dopingimpurities (D) in the layer of silicon and the superficial layer, byusing the bogus gate as an implantation mask, and replacement of thebogus gate (50) by a definitive gate, insulated by a gate dielectriclayer (52).
 4. The process as claimed in claim 3, wherein the definitivegate (50) is formed by depositing a gate material on a gate dielectriclayer, then by planarizing the gate material until the gate brushes thesuperficial layer (28).
 5. The process as claimed in claim 1, whereinstage c) comprises: production of a definitive gate (50), made of arefractory material, and implantation of doping impurities, by using thedefinitive gate as an implantation mask to form the regions of sourceand drain.
 6. The process as claimed in claim 1, wherein stage a)comprises: formation, on a first substrate, of the superficial layer(28) made of a material having a unit cell parameter close to silicon,formation, by epitaxy, of a thin layer of silicon (26) on thesuperficial layer, and transfer of the thin silicon layer and of thesuperficial layer on the insulating support (14), by making the thinlayer of silicon (26) integral with said insulating support (14).
 7. Theprocess as claimed in claim 6, wherein the transfer comprises thefracture of one of the superficial layer and of the first substrate. 8.The process as claimed in claim 1, wherein the material of thesuperficial layer is SiGe or SiGeC.
 9. The process as claimed in claim1, wherein stage b) comprises a first dry, anisotropic etching, and asecond wet etching, the dry etching being interrupted before completeelimination of the superficial layer (28) in the channel region, and thesecond etching having a selectivity greater than the selectivity of thefirst etching and being followed up with a stop on the silicon layer(26).
 10. A field effect transistor comprising: a channel (46) formed ina thin layer of monocrystalline silicon, regions of source and drain(42, 44), extending on both sides of the channel in the silicon layer(26) and in a superficial semi-conductor layer (28) covering the layerof silicon, the semi-conductor layer having a unit cell parameter closeto silicon, and an insulating gate (50), disposed above the channel, thegate being flush so as to brush the superficial layer.
 11. Thetransistor as claimed in claim 10, wherein the superficial layer is alayer of SiGe.